1. Field of the Invention
The present invention relates to a differential amplifier which is utilized in a semiconductor integrated circuit and especially useful in a GaAs integrated circuit.
2. Description of the Related Art
A semiconductor integrated circuit using GaAs as a semiconductor has received attention as an integrated circuit which can be principally operated at a speed higher than that of a semiconductor integrated circuit using Si as a semiconductor. For this reason, a device requiring a high speed operation is frequently constituted by semiconductor integrated circuits using GaAs. For example, a high-speed memory device such as an SRAM (Static Random Access Memory) is constituted by semiconductor integrated circuits consisting of MESFETs (Metal Semiconductor Field Effect Transistors) using GaAs as a semiconductor. As the SRAM, a semiconductor circuit having an E/D arrangement using a normally off type FET (to be referred to as an EFET hereinafter) as a driver and using a normally on type EFT (to be referred to as a DFET hereinafter) as a load is generally used.
FIG. 6 is a block diagram showing a schematic arrangement of an SRAM.
The SRAM approximately consists of a memory cell array 1, a sense amplifier 4, and an output buffer 5. Data of the memory cell array 1 are selected by an X-address decoder 2 and a Y-address decoder 3 and read out to bit lines. Small output signals on the bit lines are amplified and transferred to the output buffer 5.
In the SRAM with the above arrangement, the most important circuit for deciding its performance is the sense amplifier 4. The sense amplifier 4 detects and amplifies a difference .DELTA.V.sub.1 (=V.sub.1H -V.sub.1L) between an output V.sub.1H of "H" level on one of the pair of bit lines and an output V.sub.1L of "L" level on the other of the pair of bit lines. Therefore, the performance of the sense amplifier 4 depends on whether it can detect the small difference .DELTA.V.sub.1 or not. As an index representing this performance, a sensitivity is used. The sensitivity is defined as a minimum difference .DELTA.V.sub.1 required to output a signal capable of surely performing an ON/OFF operation of the sequential output buffer. For example, when a signal s having the difference .DELTA.V.sub.1 =0.1 V is input to the sense amplifier, the sense amplifier can surely output the signal s capable of surely performing an ON/OFF operation of the sequential output buffer. In this case, the sensitivity is given by 0.1 V or less.
As a register or the like used in a microprocessor, an SRAM having the arrangement shown in FIG. 6 is not used, and an SRAM having two read systems shown in FIG. 7 is frequently used. This SRAM has the following difference from the above-described SRAM. That is, input terminal of a sense amplifier 4.sub.1 and to one input terminal of a sense amplifier 4.sub.2, respectively, and a reference potential V.sub.ref is applied to the other input terminal of each of the sense amplifiers 4.sub.1 and 4.sub.2. In this case, a sensitivity .DELTA.V.sub.1 is represented by a difference .vertline.V.sub.in -V.sub.ref .vertline. between the input potential V.sub.in (V.sub.1L or V.sub.1H) and the reference potential V.sub.ref.
FIG. 8 shows a basic arrangement of a differential amplifier having an E/D arrangement and used as a sense amplifier of the above-described SRAM. This differential amplifier consists of driver EFETs Q.sub.1 and Q.sub.2 having sources commonly connected to a current source DFET Q.sub.5 and load DFETs Q.sub.3 and Q.sub.4. The input/output transfer characteristics of the differential amplifier are largely changed depending on an amount of current capacity of FETs used in the differential amplifier (Published Unexamined Japanese Patent Application No. 59-162688). When the differential amplifier is used as a sense amplifier, in order to increase its sensitivity, it is desirable that the current capacity between the driver EFETs Q.sub.1 and Q.sub.2 is equal to that between the load DFETs Q.sub.3 and Q.sub.4. In the differential amplifier having the above arrangement, when a satisfactory sensitivity is to be obtained, an "L" level output is undesirably raised.
FIG. 9 shows a differential amplifier made to solve the above problem of raising the "L" level output (Published Unexamined Japanese Patent Application No. 59-162688). As a feature of the differential amplifier, a source follower circuit is provided to the output of the differential amplifier in FIG. 8 to have a function of a level shift. That is, source follower EFETs Q.sub.6 and Q.sub.7 are connected to output terminals s of the differential amplifier, respectively. The source of the EFET Q.sub.6 is connected to a pull-down load DFET Q.sub.8 through level shift diodes D.sub.11 and D.sub.12 consisting of Schottky diodes, and the source of the EFET Q.sub.7 is connected to a pull-down loading DFET Q.sub.9 through level shift diodes D.sub.21 and D.sub.22 consisting of Schottky diodes.
FIG. 10 shows an operating waveform of the differential amplifier in FIG. 9. When a node between outputs V.sub.01 and V.sub.02 has a capacitance load of 70 fF, this operating waveform is obtained by measuring the two outputs V.sub.01 and V.sub.02 under the conditions of VDD=2 V, -0.4 V +V.sub.ref .ltoreq.V.sub.in .ltoreq.0.4 V+V.sub.ref, and V.sub.ref =1.6 V. In this case, the gate width and the threshold value of the FETs are summarized in Table 1.
TABLE 1 ______________________________________ Gate Width Threshold Value ______________________________________ Q.sub.1, Q.sub.2 10 .mu.m 0.1 V Q.sub.3, Q.sub.4 15 .mu.m -0.3 V Q.sub.5 30 .mu.m -0.3 V Q.sub.6, Q.sub.7 30 .mu.m 0.1 V Q.sub.8, Q.sub.9 15 .mu.m -0.3 V ______________________________________
In FIG. 10, a difference between the time when curves of the potentials V.sub.in and V.sub.ref are crossed and the time when potential differences between the threshold value (0.3 V) of the output buffer with an E/D arrangement and the potentials V.sub.01 and V.sub.02 are to be 0.15 V is defined as a delay time .tau.d. In this case, the delay time .tau.d is set up to 370 psec. Since the operating speed of the SRAM is controlled by the operating speed of the sense amplifier, in order to further increase the operating speed of the SRAM, the delay time of the sense amplifier is desirably shortened.
When the differential amplifier in FIG. 9 is integrated in fact, an operating range is disadvantageously small for divergence of the threshold value of an element. This phenomenon is described below with reference to FIG. 11.
In FIG. 11, the abscissa denotes a threshold value (design value of 0,1 V) V.sub.th of the EFET of the differential amplifier in FIG. 9, the ordinate denotes a threshold value (design value of -0.3 V) V.sub.th of the DFET in the differential amplifier, and a region A denotes a region where the differential amplifier can be operated, i.e., an allowable region for changing the threshold value s. In the region A, a region B indicated by hatched lines denotes a region where the differential amplifier can be operated even when an input potential difference .vertline.V.sub.in -V.sub.ref .vertline. is set to be 0.1 V, i.e., a region where a sensitivity is set to be 0.1 V or less. As shown in FIG. 11, when the threshold value V.sub.th is shifted by only 0.1 V from -0.3 V to be -0.4 V, the sensitivity of 0.1 V cannot be obtained.